TABLE OF CONTENTS
Chapter 1: Introduction
1.1. Logic Gates and Boolean Algebra
1.2. Boolean and Logic Gate Reduction
1.3. Sequential Circuits
1.4. Voltage and Current Laws
1.4.1. Terminal Resistance by Inspection
1.4.2. Node Voltage Analysis by Inspection Using Voltage Dividers
1.4.3. Branch Current Analysis by Inspection Using Current Dividers
1.4.4. Mixing Voltage and Current Dividers
1.5. Power Loss in Resistors
1.6. Capacitance
1.6.1 Capacitor Energy and Power
1.6.2 Capacitor Voltage Dividers
1.7. Inductance
1.8. Diodes
1.8.1 Diode Resistor Analysis
1.9. Some Words About Power
1.10. Summary
Chapter 2 Semiconductor Physics
2.1 Semiconductor Fundamentals
2.1.1 Metals, Inductors, and Semiconductors
2.1.2 Carriers in Semiconductors: Electrons and Holes
2.2 Intrinsic and Extrinsic Semiconductors
2.2.1 n-Type Semiconductors
2.2.2 p-Type Semiconductors
2.2.3 Carrier Concentration with n- and p-doped semiconductors
2.3 Carrier Transport
2.3.1 Drift Current
2.3.2 Diffusion Current
2.4 The pn Junction
2.5 Biasing the pn Junction
2.5.1 pn Junction Under Forward Bias
2.5.2 pn Junction Under Revcrse Bias
2.6 Diode Junction Capacitance
2.7 Summary
Chapter 3 MOSFET Transistors
3.1 Principles of Operation
3.1.1 The MOSFET as a Digital Switch
3.1.2 Physical Structure of MOSFETs
3.1.3 MOS Transistor Operation: A Descriptive Approach
3.1.4 nMOS Input Characteristics
3.1.5 nMOS Output Characteristics
3.1.6 pMOS Output Characteristics
3.2 Threshold Voltage in MOS Transistors
3.3 Summary
Chapter 4 Metal Interconnect Properties
4.1 Interconnections
4.2 Metal Resistance
4.2.1 Resistance and Thermal Effects
4.2.2 Sheet Resistance
4.2.3 Via Resistance
4.3 Capacitance
4.3.1 Capacitive Power Review
4.4 Inductance
4.4.1 Charging and Discharging Inductors
4.4.2 Inductive Power
4.5 Interconnect Models
4.5.1 C-Model for Short Lines
4.5.2 RC Model (Elmore)
4.6 Summary
Chapter 5 CMOS Inverter
5.1 The CMOS Inverter
5.1.1 Inverter Static Operation
5.2 Noise Margins
5.3 Voltage and Current Transfer Curves
5.3.1 Symmetrical Voltage Transfer Curves
5.3.2 Current Characteristics
5.4 Graphical Analysis of Bias Regions
5.4.1 Static Transfer Curves
5.4.2 Dynamic Transfer Curves
5.5 Inverter Transition Speed Model
5.6 CMOS Inverter Power
5.6.1 Transient Power (CL)
5.6.2 Short Circuit Power
5.7 Power and Power Supply Scaling
5.8 Sizing Inverter Buffers to Drive Large Loads
5.9 Summary
Chapter 6 CMOS NAND, NOR, and Transmission Gates
6.1 NAND Gate
6.1.1 NAND Gate Transistor Sizing
6.2 NOR Gate
6.2.1 NOR Gate Transistor Sizing
6.3 Pass Gates and CMOS Transmission Gates
6.3.1 Pass Gates
6.3.2 CMOS Transmission Gates
6.3.3 Tri-State Transmission Gates
6.4 Summary
Chapter 7 CMOS Design Styles
7.1 CMOS Static Logic
7.1.1 Synthesis of DeMorgan Circuits
7.2 Dynamic CMOS Logic
7.2.1 Dynamic CMOS Properties
7.2.2 Charge Sharing in Dynamic Circuits
7.3 Domino Dynamic CMOS Logic
7.4 NORA CMOS Logic
7.5 Pass Transistor Logic
7.6 CMOS Transmission Gates
7.7 Power and Activity Coefficient
7.8 Summary
Chapter 8 Sequential Logic Gate Design and Timing
8.1 Latches
8.1.1 CMOS Clocked Latches
8.1.2 Gated Latches
8.1.3 CMOS Latch with Transmission Gates
8.2 Edge-Triggered Storage Element
8.3 Timing Rules for Edge-Triggered Flip-Flop
8.4 tsu and thold with Delay Elements
8.5 Edge-Triggered Flip-Flop with Set and Reset
8.6 Clock Generation Circuitry
8.7 Metal Interconnect
8.8 Timing Skew and Jitter
8.9 Overall System Timing in Chip Design
8.10 Timing and Environmental Noise
8.11 Summary
Chapter 9 Memory Circuits
9.1 Memory Circuit Organization
9.2 Memory Cell
9.3 Decoders
9.3.1 Row Decoders
9.3.2 Column Decoders
9.4 The Read Operation
9.4.1 Width to Length Ratio Design for Read Operation
9.5 The Write Operation
9.5.1 Cell and Write Operation
9.5.2 Latch Transfer Curve
9.5.3 Write Operation Sizing
9.5.4 Column Write Circuits
9.6 Read Operation and Sense Amplifier
9.7 Dynamic Memories (DRAMs)
9.7.1 3-Transistor DRAM Cell
9.7.2 1-Transistor DRAM Cell
9.8 Conclusion
CHAPTER 10 Programmable Logic – FPGAs
10.1 A simple Programmable Circuit – The PLA
10.1.1 Programmable logic gates
10.1.2 AND/OR matrix gates – The PLA
10.2 The next step: implementing sequential circuits – The CPLDs
10.2.1 Incorporating Sequential Blocks – The Complex Programmable Logic Device (CPLD)
10.2.2 Advanced CPLDs
10.3 Advanced Programmable Logic Circuits – The FPGA
10.3.1 Actel ACT FGPAs
10.3.2 Xilinx Spartan FPGAs
10.3.3 Altera Cyclone III FPGAs
10.3.4 Today FPGAs
10.3.5 Working with FPGA’s – Design Tools
10.4 Understanding the Programmable technology
10.4.1 Antifuse technology
10.4.2 EEPROM Technology
10.4.3 Static RAM switch technology
10.5 References
Chapter 11 CMOS Circuit Layout
11.1 Layout and Design Rules
11.2 Layout Approach: Boolean Equations, Transistor Schematic, and Stick Diagrams
11.3 Laying Out a Circuit with PowerPoint
11.4 Design Rules and Minimum Spacing
11.4.1 p-MOS Transistor Layout
11.4.2 Revisiting the Design Rules of the p-MOS transistor Layout
11.4.3 n-MOS Transistor Layout
11.4.4 Merged Transistors to a Common Polygate
11.5 Completed CMOS Inverter Drawn to Design Rule Minimum Dimensions
11.6 Multi-Input Logic Gate Layouts
11.6.1 2NAND Gate Layout
11.7 Merging Logic Gate Standard Cell Layouts
11.8 More on Layout
11.9 Layout Computer Aided Design (CAD) Tools
11.10 Conclusion
Chapter 12 How Chips are Made
12.1 IC Fabrication Overview
12.2 Wafer Construction
12.3 Front and Back End of Line Fabrication
12.4 Front End of Line (FOL) Fab Techniques
12.4.1 Oxidation of Silicon
12.5 Photolithography
12.5.1 Etching
12.5.2 Deposition
12.5.2.1 Chemical Vapor Deposition
12.5.2.2 Ion-Implantation
12.5.2.3 Diffusion
12.6 Cleaning and Safety Operations
12.7 Transistors
12.8 Back End of Line (BOL) Fab Techniques
12.8.1 Sputtering
12.8.2 Dual Damascene
12.8.3 Interlevel Dielectric and Final Passivation
12.9 Fabricating a CMOS Inverter
12.9.1 Front End of Line Operation
12.9.2 Back End of Line Operation
12.10 Packaging
12.11 IC Testing
12.12 Conclusion
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